1. Field of the Invention
The present invention relates to a quadrature demodulator equipped with a Phase-Locked Loop (PLL) and more particularly, to a quadrature demodulator equipped with a PLL section for stabilizing the oscillation frequency of the oscillator for the carrier frequency, which is applicable to digital communication and/or digital broadcast.
2. Description of the Related Art
With digital communication and digital broadcast, the system of Quadrature Phase Shift Keying (QPSK) is often used. QPSK is one of digital modulation systems, which is explained below.
With the QPSK system, the baseband signal containing the information to be transmitted is mixed with two carrier signals having the same frequency and a phase difference of 90xc2x0 (i.e., two orthogonal carrier signals) in frequency mixers, generating two orthogonal modulated signals. These two modulated signals, which are Binary PSK (BPSK) signals, are termed the xe2x80x9cin-phase modulated signalxe2x80x9d (i.e., I-modulated signal) and the xe2x80x9cquadrature-phase modulated signalxe2x80x9d (i.e., Q-modulated signal). The I- and Q-modulated signals thus generated are added or synthesized together by an adder, forming the QPSK modulated signal.
To demodulate the QPSK modulated signal, two carrier signals having the same frequency as the QPSK modulated signal and a phase difference of 90xc2x0 to each other are generated in a receiver, thereby generating two orthogonal carrier signals. The QPSK modulated signal is mixed with the two orthogonal carrier signals thus generated by frequency mixers in the receiver, thereby forming two orthogonal BPSK demodulated signals (i.e., an xe2x80x9cI-demodulated signalxe2x80x9d and a xe2x80x9cQ-demodulated signalxe2x80x9d). The I- and Q-demodulated signals thus formed are demodulated by a detector in the receiver according to the specified detection method (e.g., delayed detection or synchronous detection) Thus, the baseband signal containing the information to be transmitted is reproduced.
On the other hand, with digital mobile telephones and satellite broadcasting receivers, the double conversion method is usually used. With the double conversion method, the Radio-Frequency (RF) received signal is converted into an Intermediate-Frequency (IF) signal. Next, unnecessary signals contained in the IF signal are removed and then, the IF signal is converted into the baseband signal. Thus, the information in the baseband signal is reproduced in the receiver side.
Various types of quadrature demodulators have ever been developed for digital mobile telephones and satellite broadcasting receivers to demodulate the QPSK modulated signal according to the Double Conversion method. An example of the quadrature demodulators is shown in FIG. 1, which is designed for receiving the signal from the Direct Broadcast Satellite (DBS).
As seen from FIG. 1, the prior-art quadrature demodulator comprises a quadrature demodulator section 110, an oscillator 120, a PLL section 130, and a resonant circuit 140. The demodulator section 110, the oscillator 120, and the PLL section 130 are provided on the Integrated Circuit (IC) 101 of the quadrature demodulator. The resonant circuit 140 is provided outside the IC 101.
An input IF signal SIF with a specific intermediate frequency (e.g., 480xc2x130 MHz) is inputted into the input terminal TIN of the prior-art quadrature demodulator. The input signal SIF thus inputted is sent to the quadrature demodulator section 110 on the IC 101 by way of a capacitor C11 and a terminal T1.
In the quadrature demodulator section 110, an IF amplifier 111 amplifies the input signal SIF to generate an amplified IF signal SIFA. The IF signal SIFA thus generated is sent to an I-signal mixer 112 and a Q-signal mixer 114. The I-signal mixer 112 frequency-converts the IF signal SIFA to generate a baseband I signal SBI. The, Q-signal mixer 114 frequency-converts the IF signal SIFA to generate a baseband Q signal SBQ.
Specifically, the quadrature demodulator section 110 comprises a frequency multiplier 117 and a 90xc2x0-phase shifter 116. The frequency multiplier 117 doubles a local frequency fLOC (e.g., 479.5 MHz) of a local signal (i.e., the carrier signal) sent from the oscillator 120, forming a signal SLOC2 with a doubled frequency 2fLOC (e.g., 959 MHz). The 90xc2x0 phase shifter 116 frequency-divides the signal SLOC2 thus formed and phase-shifts the same by 90xc2x0, generating a local I signal SLOCI with the frequency fLOC and a local Q signal SLOCQ with the same frequency fLOC. Then, the phase shifter 116 sends the local I signal SLOCI with the 0xc2x0-phase to an I signal mixer 112 and the local Q signal SLOCQ with the 90xc2x0 phase to a Q signal mixer 114.
The I signal mixer 112 mixes the amplified IF signal SIFA sent from the IF amplifier 111 with the local I signal SLOCI sent from the phase shifter 116, generating a baseband I signal SBI with the 0xc2x0-phase. Similarly, the Q signal mixer 114 mixes the amplified IF signal SIFA sent from the IF amplifier 111 with the local Q signal SLOCQ sent from the phase shifter 116, generating a baseband Q signal SBQ with the 90xc2x0 phase. The baseband I and Q signals SBI and SBQ have the same frequency (e.g., 30 MHz).
Baseband amplifiers 113 and 115 amplify the baseband I and Q signals SBI and SBQ, thereby producing amplified baseband I and Q signals SBIA and SBQA, respectively. The amplified baseband I and Q signals SBIA and SBQA thus produced are outputted from the IC 101 by way of its terminals T2 and T3, respectively. Then, the amplified baseband I and Q signals SBIA and SBQA are further outputted from the output terminals TOUT1 and TOUT2 of the prior-art quadrature demodulator by way of capacitors C12 and C13 as the baseband output I and Q signals SBIO and SBQO, respectively. The baseband output I and Q signals SBIO and SBQO thus outputted are sent to a detector (not shown) in a next stage.
The oscillator 120 and the resonant circuit 140 cooperate to generate the local signal SLOC with the specified local frequency fLOC. The oscillation frequency of the oscillator 120, which is equal to the local frequency fLOC, can be set and varied by adjusting the resonant frequency of the resonant circuit 140.
The resonant circuit 140, which is located outside the demodulator IC 101, comprises a varactor diode BD capable of changing its capacitance according to an applied voltage, an inductor L11, and six capacitors C14, C15, C16, C17, C18, and C19. A resistor R11, which is connected between the varactor diode BD and a terminal T9 of the IC 101, serves to prevent excess currents from flowing through the diode BD. Similarly, a resistor R12, which is connected between the varactor diode BD and the ground, serves to prevent excess currents from flowing through the diode BD. The resonant circuit 140 having such a configuration is connected to the oscillator 120 by way of four terminals T5, T6, T7, and T8 of the IC 101.
The PLL section 130 comprises a prescaler 131, a counter 132, a frequency divider 133, a phase comparator 134, a charge pump 135, and a Direct Current (DC) amplifier 136. The PLL section 130 compares the local frequency fLOC of the local signal SLOC with the reference frequency fREF of a reference signal SREF produced by a quartz oscillator X11, thereby stabilizing the local frequency fLOC against the change in the power supply voltage and the ambient temperature. The quartz oscillator X11 is provided outside the IC 101 and connected to its terminal T4.
The prescaler 131 serves as a frequency divider for dividing an incoming frequency by N1, where N1 is a positive constant. The prescaler 131 receives the local signal SLOC sent from the oscillator 120 and produces a signal SPS with a divided frequency (fLOC/N1) The
The counter 132 serves as a frequency divider for dividing an incoming frequency by N2, where N2 is a positive constant. The counter 132 receives the signal SPS sent from the prescaler 131 and produces a signal SC with a divided frequency (fLOC/N1N2)The
The frequency divider 133 receives the reference signal SREF sent from the quartz oscillator X11 and produces a signal SREFD with a divided frequency (fREF/N3), where N3 is a positive constant.
The phase comparator 134 compares the phase of the signal SC sent from the counter 132 with that of the signal SREFD sent from the frequency divider 133, outputting a signal SPC proportional to the phase difference between the signals SC and SREFD.
The charge pump 135 detects the signal SPC sent from the phase comparator 134 and rectifies the same, forming a rectified signal SCP1. The rectified signal SCP1 thus formed is sent to the DC amplifier 136. An Alternating Current (AC) component SCP2 in the rectified signal SCP1 is sent to the ground by way of a capacitor C20, thereby canceling the AC component SCP2 from the signal SCP1. The capacitor C20, which is connected to the IC 101 by way of its terminal T10, serves as a low pass filter.
The DC amplifier 136 amplifies the DC signal SCP1 to produce an amplified DC voltage signal SCPA.
The amplified DC voltage signal SCPA produced by the amplifier 136 is sent to the varactor diode BD of the resonant circuit 140 through the terminal T10 as a tuning voltage for the diode BD. The capacitance value of the diode BD is changed according to the voltage value of the signal SCPA and therefore, the resonant frequency of the circuit 140 is varied. As a result, the oscillation frequency (i.e., the local frequency) fLOC of the oscillator 120 is adjusted finely or minutely. In other words, the oscillation or local frequency fLOC varies according to the voltage value change of the amplified DC voltage signal SCPA as the output of the PLL section 130. Thus, the oscillation or local frequency fLOC generated by the oscillator 120 can be kept at a specific constant value even if the change of the power supply voltage and/or the change of the ambient temperature occurs.
However, the prior-art quadrature demodulator described above with reference to FIG. 1 has the following problems.
The first problem is that the circuit configuration of the quadrature demodulator section 110 is complicated. This is because the section 110 comprises the frequency multiplier 117 for doubling the local frequency fLOC of the local signal SLOC outputted from the oscillator 120.
The second problem is that a considerable number of components or parts are required in addition to the demodulator IC 101, which increases the fabrication cost. This is because the variable resonant circuit 140 is provided outside the IC 101 and connected the same in order to stabilize the oscillation frequency fLOC of the oscillator 120, where the resonant circuit 140 necessitates the varactor diode BD, the inductor L11, the capacitors C14 to C19, and the resistors R11 and R12.
The third problem is that the operation for adjusting or optimizing the oscillation characteristic of the oscillator 120 (and thus, the demodulation characteristic of the prior-art demodulator itself) requires considerable labor (i.e., man-hours) and considerable time. This is due to the considerable number of components or parts being required for the prior-art demodulator. This problem increases the fabrication cost as well.
The Japanese Non-Examined Patent Publication No. 8-317002 published in November 1996 discloses a configuration that an oscillator whose oscillation frequency is twice the desired local frequency is provided on the same device as a quadrature demodulator section, thereby canceling the frequency multiplier from the quadrature demodulator section. This configuration solves the above-described first problem; however, it is unable to solve the above-described second and third problems.
Accordingly, an object of the present invention is to provide a quadrature demodulator that simplifies the circuit configuration of a quadrature demodulator section and that reduces the labor or man-hours and the time required for adjusting the demodulation characteristic.
Another object of the present invention is to provide a quadrature demodulator that decreases the number of components or parts required and lowers the fabrication cost.
Still another object of the present invention is to provide a quadrature demodulator that reduces the number of components or parts necessarily provided outside a device (e.g., an IC and a module) including a quadrature demodulator section, an oscillator section, and a PLL section.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
A quadrature demodulator according to the present invention is comprised of:
(a) an oscillator section for generating a local signal with a local frequency of twice a carrier frequency;
(b) a quadrature demodulator section for generating two orthogonal baseband signals by frequency-converting an input signal with a specific frequency using the,local signal;
(c) a PLL section for stabilizing the local frequency by applying its output signal corresponding to a difference between the local frequency of the local signal and a predetermined reference frequency to the oscillator section;
(d) the oscillator section having an oscillator capable of varying its oscillation frequency by changing its driving current, the driving current being changeable according to the output signal of the PLL section; and
(e) the local frequency of the local signal being kept constant by adjusting the driving current of the oscillator section by way of the output signal of the PLL section.
With the quadrature demodulator according to the present invention, the oscillator section generates the local signal with the local frequency of twice the carrier frequency and then, the quadrature demodulator section generates the two orthogonal baseband signals by frequency-converting the input signal with the specific frequency using the local signal. Thus, the quadrature demodulator section necessitates no frequency multiplier and as a result, the configuration of the quadrature demodulator section is simplified.
A circuit for generating two orthogonal signals through the frequency-division operation of the local frequency equal to twice the carrier frequency by two and the phase-shifting operation of the signal thus frequency-divided by 90xc2x0 can be easily configured with, for example, at least one T-type flip-flop circuit triggered at each leading edge of an input signal and at least one T-type flip-flop circuit triggered at each trailing edge thereof. Accordingly, even if the local signal with the local frequency equal to twice the carrier frequency is applied to the quadrature demodulator section, the configuration of the quadrature demodulator section can be simpler than the configuration with a frequency multiplier.
Moreover, the oscillator section has the oscillator capable of varying its oscillation frequency by changing its driving current while the driving current is changeable according to the output signal of the PLL section. In other words, the oscillator is of the current-driven type, which is unlike the previously-described prior-art quadrature demodulator comprising the oscillator of the voltage-driven type. Therefore, the oscillation frequency (i-e., the local frequency) of the oscillator can be adjusted without using any capacitance-variable resonator. As a result, the labor or man-hours and the time required for adjusting the demodulation characteristic can be reduced.
Additionally, a complicated circuit (e.g., a capacitance-variable resonator) cooperating with the oscillator section is unnecessary. Alternately, it is sufficient for the resonator to have a fixed resonant frequency. Thus, the number of components or parts required for the quadrature demodulator is decreased and at the same time, the fabrication cost of the quadrature demodulator is lowered.
If the quadrature demodulator has a configuration that the quadrature demodulator section, the oscillator section, and the PLL section are provided on a device (e.g., an IC and a module), the number of components or parts necessarily provided outside the device can be reduced.
In a preferred embodiment of the demodulator according to the invention, a resonant circuit with a fixed resonant frequency is additionally provided. Theresonant circuit cooperates with the oscillator section to generate the local signal. In this case, it is preferred that the resonant circuit is a LC resonant circuit (e. g., a so-called xe2x80x9cLC tankxe2x80x9d) including an inductor and a capacitor.
In another preferred embodiment of the demodulator according to the invention, the oscillator section includes a resonant circuit with a fixed resonant frequency.
In still another preferred embodiment of the demodulator according to the invention, the oscillator section includes a variable current source for generating the variable driving current. A value of the current generated by the current source is controlled by the output signal of the PLL section.
In a further preferred embodiment of the demodulator according to the invention, a resonant circuit with a fixed resonant frequency is additionally provided. The resonant circuit cooperates with the oscillator section to generate the local signal. The resonant circuit is provided outside the oscillator section and connected to the same.
In a still further preferred embodiment of the demodulator according to the invention, a resonant circuit with a fixed resonant frequency is additionally provided. The resonant circuit cooperates with the oscillator section to generate the local signal. The resonant circuit is provided in the oscillator section. In this embodiment, there is an additional advantage that the operation of connecting the resonant circuit to the oscillator section is unnecessary and thus, the number of the required components or parts is decreased furthermore.